Bug 17484 – high penalty for vbroadcastsd with -mcpu=avx

With -mcpu=avx, the compiler emits vbroadcastsd ymm2, qword ptr [rsp] even when initializing only 128-bit wide double2 variables. This causes a high 50-80 cycle penalty when later some legacy SSE instruction is used with such a register value (or a derived value), because the CPU does not know that the upper bits are zero, and apparently preserves them in an internal register buffer. https://software.intel.com/en-us/articles/intel-avx-state-transitions-migrating-sse-code-to-avx We should A not write to 256-bit wide YMM registers when only 128-bit wide XMM registers are used, and B avoid mixing legacy encoded SSE instructions (movsd) with vex encoded AVX-128 instructions, i.e. use vmovsd instead of movsd.

Commit pushed to master at https://github.com/dlang/dmd https://github.com/dlang/dmd/commit/1f11aa0eb8f6087b7dbadeb770e4526ec9808ccc fix Issue 17484 - high penalty for AVX-256 instructions with AVX-128 regs - as the upper 128-bits are no longer zero, the CPU will save/restore them when that register is used with legacy SSE instructions - avoid using vbroadcastsd which is a AVX-256 only instruction to initialize 128-bit XMM vectors

Commit pushed to newCTFE at https://github.com/dlang/dmd https://github.com/dlang/dmd/commit/1f11aa0eb8f6087b7dbadeb770e4526ec9808ccc fix Issue 17484 - high penalty for AVX-256 instructions with AVX-128 regs

Commit pushed to stable at https://github.com/dlang/dmd https://github.com/dlang/dmd/commit/1f11aa0eb8f6087b7dbadeb770e4526ec9808ccc fix Issue 17484 - high penalty for AVX-256 instructions with AVX-128 regs