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Bug 20055 – 128 byte-alignment cache padding for AlignedSpinLock on x86_64?

Status
NEW
Severity
enhancement
Priority
P4
Component
druntime
Product
D
Version
D2
Platform
x86_64
OS
All
Creation time
2019-07-15T16:53:58Z
Last change time
2024-12-07T13:39:26Z
Assigned to
No Owner
Creator
Hiroki Noda
Moved to GitHub: dmd#17386 →

Comments

Comment #0 by kubo39 — 2019-07-15T16:53:58Z
Accroding to Intel® 64 and IA-32 Architectures Optimization Reference Manual https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf > 2.3.5.4 Data Prefetching > Spatial Prefetcher: This prefetcher strives to complete every cache line fetched to the L2 cache with > the pair line that completes it to a 128-byte aligned chunk. Maybe it's better to use 128-byte alignment for core.internal.spinlock.AlignedSpinLock on x86_64?
Comment #1 by robert.schadek — 2024-12-07T13:39:26Z
THIS ISSUE HAS BEEN MOVED TO GITHUB https://github.com/dlang/dmd/issues/17386 DO NOT COMMENT HERE ANYMORE, NOBODY WILL SEE IT, THIS ISSUE HAS BEEN MOVED TO GITHUB