Bug 5885 – wrong codegen for OPu32_d

Status
RESOLVED
Resolution
FIXED
Severity
critical
Priority
P2
Component
dmd
Product
D
Version
D2
Platform
x86_64
OS
All
Creation time
2011-04-25T07:32:00Z
Last change time
2011-06-28T15:00:31Z
Keywords
patch, wrong-code
Assigned to
nobody
Creator
code

Attachments

IDFilenameSummaryContent-TypeSize
9480001-fix-OPu32_d-codegen.patchpatchtext/plain1235
9880001-OPu32_d-codegen.patchnew fixtext/plain1148

Comments

Comment #0 by code — 2011-04-25T07:32:40Z
Created attachment 948 patch struct Value { uint a, b; } double mul(Value val, double fac) { return val.a * fac; } int main() { auto a = mul(Value(10), 10.0); // seems to work as val.b == 0 auto b = mul(Value(10, 20), 10.0); // loads the 20 in the fpu return a == b ? 0 : 1; } -- What happens is that the complete rdi register gets pushed and a 64 bit integer is loaded from that address to the FPU. Maybe I'm missing something but loading an 32 bit simplifies even the 32-bit code. See attached patch.
Comment #1 by code — 2011-05-21T05:08:47Z
Created attachment 988 new fix The proposed patch was wrong. FILD m64int needs to be used as there are no unsigned->fpu load instructions. The new patch explicitly zeros the upper 4 bytes.
Comment #2 by bugzilla — 2011-06-28T15:00:31Z