The inline assembler does not work very well if the registers R8..R15 are used.
Some instructions such as mov RAX,[RBX+1*R13] generate working code.
The compiler does not accept mov RAX,[R13]
Other variations such as mov RAX,[0+1*R11] generate the wrong code (generates an instruction for RBX instead of R11).
Compiler version:
DMD64 D Compiler v1.069
Comment #1 by grahamc001uk — 2011-08-31T10:08:18Z
DMD64 D Compiler v2.054 has exactly the same problem.
Comment #2 by braddr — 2011-08-31T10:13:56Z
I suspect this is already fixed in git and will go out with the next release.
Comment #3 by grahamc001uk — 2011-09-11T04:28:05Z
The above still present in v2.055
I also notice if you do:
and RAX,0x00000000FFFFFFFF
the compiler accepts it but generates:
and RAX,0xFFFFFFFFFFFFFFFF
because, of course, there is no imm64 mode for and/or etc. instructions.
Same applies for all other immediate constants that can be encoded into 8 bits.
Comment #4 by grahamc001uk — 2011-09-11T09:48:23Z
Another negative immediate value issue:
mov EAX,-2; /* line 1 */
mov EAX,0xFFFFFFFE; /* line 2 */
mov EAX,0xFFFFFFFFFFFFFFFE; /* line 3 */
mov R8D,-2; /* line 4 */
mov R8D,0xFFFFFFFE; /* line 5 */
mov R8D,0xFFFFFFFFFFFFFFFE; /* line 6 */
Anybody writing line 3 or 6 has probably made a mistake, but line 3 is accepted as equivalent to 1 and 2, and line 6 is accepted as equivalent to 4 and 5 (as 32 bit loads clear the top 32 bits of the equivalent 64 bit register they do not sign extend).
Comment #5 by safety0ff.bugz — 2015-04-04T22:29:54Z
> I also notice if you do:
> and RAX,0x00000000FFFFFFFF
> the compiler accepts it but generates:
> and RAX,0xFFFFFFFFFFFFFFFF
This bug is still present
Comment #6 by bugzilla — 2020-08-02T06:31:46Z
> Other variations such as mov RAX,[0+1*R11] generate the wrong code (generates an instruction for RBX instead of R11).
This causes an assert failure now.
Comment #7 by bugzilla — 2020-08-02T08:56:38Z
(In reply to Graham from comment #3)
> I also notice if you do:
>
> and RAX,0x00000000FFFFFFFF
>
> the compiler accepts it but generates:
>
> and RAX,0xFFFFFFFFFFFFFFFF
>
> because, of course, there is no imm64 mode for and/or etc. instructions.
> Same applies for all other immediate constants that can be encoded into 8
> bits.
The compiler generates an error for this now.
@WalterBright created dlang/dmd pull request #11489 "fix Issue 6459 - Inline asm bugs with 64 bit registers R8..R15" fixing this issue:
- fix Issue 6459 - Inline assembler does not work well for 64 bit registers R8..R15
https://github.com/dlang/dmd/pull/11489
Comment #10 by dlang-bot — 2020-08-02T19:19:15Z
dlang/dmd pull request #11489 "fix Issue 6459 - Inline asm bugs with 64 bit registers R8..R15" was merged into master:
- 7e3567eeb4ee48eb1c39f51851fa4a62e636a582 by Walter Bright:
fix Issue 6459 - Inline assembler does not work well for 64 bit registers R8..R15
https://github.com/dlang/dmd/pull/11489